25Libre-Chip Awarded NLnet Grant to Prototype a CPU Isn't Vulnerable to SpectreInteresting to see, hope they make progress on preventing the spectre attacks, since these are still relevant today. See this paper that was presented at the WHY2025 hacker camp: https://openreview.net/pdf?id=4tDNvQe2G0Speculative execution > Variants,: https://en.wikipedia.org/wiki/Speculative_executionTransient execution CPU vulnerability: https://en.wikipedia.org/wiki/Transient_execution_CPU_vulner...Does RISC-V have speculative execution?A RISC-V CPU out of graphene would be more efficient.openhwgroup has open Verilog implementations of RISC-V cores from 2 stages through 6 stages that will boot Linux: https://github.com/openhwgroupThere are various optional feature flags for RISC-V.The RISC-V open ISA is probably advantageous especially for research implementations.
Interesting to see, hope they make progress on preventing the spectre attacks, since these are still relevant today. See this paper that was presented at the WHY2025 hacker camp: https://openreview.net/pdf?id=4tDNvQe2G0
Speculative execution > Variants,: https://en.wikipedia.org/wiki/Speculative_executionTransient execution CPU vulnerability: https://en.wikipedia.org/wiki/Transient_execution_CPU_vulner...Does RISC-V have speculative execution?A RISC-V CPU out of graphene would be more efficient.openhwgroup has open Verilog implementations of RISC-V cores from 2 stages through 6 stages that will boot Linux: https://github.com/openhwgroupThere are various optional feature flags for RISC-V.The RISC-V open ISA is probably advantageous especially for research implementations.
openhwgroup has open Verilog implementations of RISC-V cores from 2 stages through 6 stages that will boot Linux: https://github.com/openhwgroupThere are various optional feature flags for RISC-V.The RISC-V open ISA is probably advantageous especially for research implementations.
Interesting to see, hope they make progress on preventing the spectre attacks, since these are still relevant today. See this paper that was presented at the WHY2025 hacker camp: https://openreview.net/pdf?id=4tDNvQe2G0
Speculative execution > Variants,: https://en.wikipedia.org/wiki/Speculative_execution
Transient execution CPU vulnerability: https://en.wikipedia.org/wiki/Transient_execution_CPU_vulner...
Does RISC-V have speculative execution?
A RISC-V CPU out of graphene would be more efficient.
openhwgroup has open Verilog implementations of RISC-V cores from 2 stages through 6 stages that will boot Linux: https://github.com/openhwgroup
There are various optional feature flags for RISC-V.
The RISC-V open ISA is probably advantageous especially for research implementations.